ARCS - Conference on Architecture of Computing Systems
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Conference Paper Enhanced reliability in tiled manycore architectures through transparent task relocation(Gesellschaft für Informatik e.V., 2012) Rauchfuss, Holm; Wild, Thomas; Herkersdorf, Andreas; Mühl, Gero; Richling, Jan; Herkersdorf, AndreasManycore platforms with tens and even up to hundreds of processing cores per chip are becoming a commercial reality and are subject of intensified research. This concept paper describes work in progress on the applicability of HW supported communication and processing virtualization on regular structured, tiled manycore architectures for the benefit of improved fault tolerance against transient and permanent perturbations. Temporarily unused, naturally redundant tiles are dynamically occupied during run time via transparent task relocation. This means, the execution of a task can pro-actively and transparently for the application be switched by distributed system management and virtualization services from a tile, which is considered unreliable, to a more reliable tile. In order to support different requirements regarding safety, timing integrity and minimized overhead for the relocation services, several established strategies can be enacted by the system management. The migration protocol for signaling during run configuration and actual relocation allows migration with minimal downtime and no communication loss. The actual migration is triggered by a configurable threshold on critical system parameters on a per task basis.Conference Paper A comparison of parallel programming models of network processors(Gesellschaft für Informatik e.V., 2004) Albrecht, Carsten; Hagenau, Rainer; Maehle, Erik; Döring, Andreas; Herkersdorf, Andreas; Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A.Today's network processor utilize parallel processing in order to cope with the traffic growth and wire-speed of current and future network technologies. In this paper, we study two important parallel programming models for network processors: run to completion and pipelining. In particular, the packet flow of a standard network application, IPv4 Forwarding, through two examined network processors, IBM PowerNP NP4GS3 and Intel IXP1200, is reviewed and characterized in respect to their programming models. Based on a benchmark for PC-cluster SANs, their application throughput and latency for Gigabit Ethernet is investigated and compared to a commercial, ASIC-based switch. It is shown that in this scenario network processors can compete with hard-wired solutions.Conference Paper Towards a dynamically reconfigurable system-on-chip platform for video signal processing(Gesellschaft für Informatik e.V., 2004) Stechele, Walter; Herrmann, Stephan; Herkersdorf, Andreas; Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A.This paper reports ongoing work towards a dynamically reconfigurable System-on-Chip (SoC) platform for video signal processing. It consists of dedicated, statically and dynamically reconfigurable components, as well as an embedded RISC core and memory. Application-specific software libraries support control of dynamic reconfiguration of low level operations by high level instructions. Thus programmability is combined with high data throughput and low power consumption of hardwired circuits. Preliminary work presented here is focused on one selected application, video object segmentation. The architecture of a coprocessor for video object segmentation is presented, which exploits the basic concept of the dynamically reconfigurable SoC platform. A library of software functions for image processing was developed, too, which will be used as a starting point for the application-specific software parts of the platform.