ARCS - Conference on Architecture of Computing Systems
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Conference Paper Levels in configurability for CRC calculation(Gesellschaft für Informatik e.V., 2006) Döring, Andreas; Karl, Wolfgang; Becker, Jürgen; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, ErikConference Paper A comparison of parallel programming models of network processors(Gesellschaft für Informatik e.V., 2004) Albrecht, Carsten; Hagenau, Rainer; Maehle, Erik; Döring, Andreas; Herkersdorf, Andreas; Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A.Today's network processor utilize parallel processing in order to cope with the traffic growth and wire-speed of current and future network technologies. In this paper, we study two important parallel programming models for network processors: run to completion and pipelining. In particular, the packet flow of a standard network application, IPv4 Forwarding, through two examined network processors, IBM PowerNP NP4GS3 and Intel IXP1200, is reviewed and characterized in respect to their programming models. Based on a benchmark for PC-cluster SANs, their application throughput and latency for Gigabit Ethernet is investigated and compared to a commercial, ASIC-based switch. It is shown that in this scenario network processors can compete with hard-wired solutions.Conference Paper Parallelism in a CRC coprocessor(Gesellschaft für Informatik e.V., 2004) Döring, Andreas; Brinkschulte, Uwe; Becker, Jürgen; Fey, Dietmar; Großpietsch, Karl-Erwin; Hochberger, Christian; Maehle, Erik; Runkler, Thomas A.Cyclic Redundancy Checks (CRC) constitute an important class of hash functions for detecting changes in data blocks after transmission, storage and retrieval, or distributed processing. Currently, most sequential methods based on Horner's scheme are applied with some extensions or modifications. The flexibility of these methods with respect to the generator polynomial and the sequence of data processing is limited. A newly proposed algorithm and architecture [DW03, DW04] offer a high degree of flexibility in several aspects and provide high performance with a modest investment in hardware. The algorithm has inherent freedom for parallel processing on several levels, which is exploited in the proposed architecture. An early implementation gives quantitative results on cost and performance and suggests possible extensions and improvements. The algorithm, a typical system architecture, and the coprocessor's structure are described in this paper with an emphasis on parallelism.